Comments on: Down With fcmp: Conditional Moves For Branchless Math http://assemblyrequired.crashworks.org/2009/01/04/fcmp-conditional-moves-for-branchless-math/ Technical Notes On Game Development Wed, 21 Jul 2010 18:22:16 -0700 http://wordpress.org/?v=2.9.2 hourly 1 By: » Stupid C++ vs C# performance comparison Florent Clairambault http://assemblyrequired.crashworks.org/2009/01/04/fcmp-conditional-moves-for-branchless-math/comment-page-1/#comment-5174 » Stupid C++ vs C# performance comparison Florent Clairambault Thu, 04 Mar 2010 18:34:17 +0000 http://assemblyrequired.crashworks.org/?p=50#comment-5174 [...] Conditional moves [...] [...] Conditional moves [...]

]]> By: Adisak http://assemblyrequired.crashworks.org/2009/01/04/fcmp-conditional-moves-for-branchless-math/comment-page-1/#comment-5026 Adisak Wed, 21 Oct 2009 22:08:31 +0000 http://assemblyrequired.crashworks.org/?p=50#comment-5026 FWIW, if you code your isel to do a mask and mask complement, it will be faster on PowerPC since the compiler is smart enough to generate an 'andc' opcode. It's the same number of opcodes but there is one fewer result-to-input-register dependency in the opcodes. The two mask operations can also be issued in parallel on a superscalar processor. It can be 2-3 cycles faster if everything is lined up correctly. return (x & (~mask)) + (y & mask); FWIW, if you code your isel to do a mask and mask complement, it will be faster on PowerPC since the compiler is smart enough to generate an ‘andc’ opcode. It’s the same number of opcodes but there is one fewer result-to-input-register dependency in the opcodes. The two mask operations can also be issued in parallel on a superscalar processor. It can be 2-3 cycles faster if everything is lined up correctly.

return (x & (~mask)) + (y & mask);

]]> By: Elan http://assemblyrequired.crashworks.org/2009/01/04/fcmp-conditional-moves-for-branchless-math/comment-page-1/#comment-4921 Elan Wed, 20 May 2009 00:13:51 +0000 http://assemblyrequired.crashworks.org/?p=50#comment-4921 In theory perhaps, but as game developers we have exactly four configurations to care about: MSVC for Windows; MSVC for XBox360; Sony-gcc for PS3; CodeWarrior for Wii. Each of these architectures sign-extends on right shift. In fact the whole discussion above is specific to the pipeline of the PPC inside the 360 and the PS3; on other platforms the situation might be entirely different. Optimization at this level really means taking advantage of the hardware and its particular implementation; if not, we wouldn't be able to use SSE or VMX or the SPU either because they're not perfectly portable. In theory perhaps, but as game developers we have exactly four configurations to care about: MSVC for Windows; MSVC for XBox360; Sony-gcc for PS3; CodeWarrior for Wii. Each of these architectures sign-extends on right shift. In fact the whole discussion above is specific to the pipeline of the PPC inside the 360 and the PS3; on other platforms the situation might be entirely different.

Optimization at this level really means taking advantage of the hardware and its particular implementation; if not, we wouldn’t be able to use SSE or VMX or the SPU either because they’re not perfectly portable.

]]> By: Sam http://assemblyrequired.crashworks.org/2009/01/04/fcmp-conditional-moves-for-branchless-math/comment-page-1/#comment-4920 Sam Tue, 19 May 2009 22:45:06 +0000 http://assemblyrequired.crashworks.org/?p=50#comment-4920 The C/C++ standards state the result of right shifts on negative signed values is undefined? I believe the correctness of your isel function is at the mercy of the compiler/hardware platform. The C/C++ standards state the result of right shifts on negative signed values is undefined? I believe the correctness of your isel function is at the mercy of the compiler/hardware platform.

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